revision 0.0 KM68512B family cmos sram january 1998 1 advance document title 64kx8 bit low power cmos static ram revision history revision no. 0.0 remark advance history initial draft draft data january 10th 1998 the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you.
revision 0.0 KM68512B family cmos sram january 1998 2 advance 64kx8 bit low power cmos static ram the KM68512B family is fabricated by samsung s advanced cmos process technology. the family support various operat- ing temperature ranges and small package type for user flexi- bility of system design. the family also support low data retention voltage for battery back-up operation with low data retention current. general description features process technology : 0.4 m m cmos organization : 64kx8 power supply voltage : single 5v 10% low data retention voltage : 2v(min) three state output and ttl compatible package type : 32-tsop i -0820f pin description name function a 0 ~a 15 address inputs we write enable input cs 1 , cs 2 chip select inputs oe output enable input i/o 1 ~i/o 8 data inputs/outputs vcc power vss ground n.c no connection product family product family operating temperature v cc range speed(ns) power dissipation pkg type standby (i sb1 , max) operating (i cc2 , max) KM68512Bl-l commercial(0~70 c) 5v 0.5v 55/70 10 m a 60ma 32-tsop1-f KM68512Bli-l industrial(-40~85 c) 70 15 m a functional block diagram samsung electronics co., ltd. reserves the right to change products and specifications without notice. a11 a9 a8 a13 we cs2 a15 nc nc a14 a12 a7 a6 a5 a4 oe a10 cs 1 i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 a3 32-tsop type1 - forward 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vcc precharge circuit. memory array 512 rows 128 8 columns i/o circuit column select clk gen. row select a0 a1 a2 a3 a9 a11 a10 a4 a5 a6 a7 a8 a12 a14 i/o1 data cont data cont i/o8 a13 a15 cs we oe control logic cs2
revision 0.0 KM68512B family cmos sram january 1998 3 advance product list commercial temperature product (0~70 c) industrial temperature products (-40~85 c) part name function part name function KM68512Blt-5l KM68512Blt-7l 32-tsop1-f, 55ns, ll-pwr 32-tsop1-f, 70ns, ll-pwr KM68512Blti-7l 32-tsop1-f, 70ns, ll-pwr functional description 1. x means don t care.(must be low or high state) cs 1 cs 2 oe we i/o pin mode power h x 1) x 1) x 1) high-z deselected standby x 1) l x 1) x 1) high-z deselected standby l h h h high-z output disabled active l h l h dout read active l h x l din write active absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.5 to 7.0 v - voltage on vcc supply relative to vss v cc -0.5 to 7.0 v - power dissipation p d 1.0 w - storage temperature t stg -65 to 150 c - operating temperature t a 0 to 70 c KM68512Bl -40 to 85 c KM68512Bli soldering temperature and time t solder 260 c, 10sec(lead only) - -
revision 0.0 KM68512B family cmos sram january 1998 4 advance recommended dc operating conditions 1) note 1. commercial product : t a =0 to 70 c, unless otherwise specified industrial product : t a =-40 to 85 c, unless otherwise specified 2. overshoot : v cc +3.0v in case of pulse width 30ns 3. undershoot : -3.0v in case of pulse width 30ns 4. overshoot and undershoot is sampled, not 100% tested item symbol min typ max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.2 - vcc+0.5v 2) v input low voltage v il -0.5 3) - 0.8 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 6 pf input/output capacitance c io v io =0v - 8 pf dc and operating characteristics 1. industrial product = 15 m a item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs 1 =v ih or cs 2 =v il or oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a operating power supply i cc i io =0ma, cs 1 =v il , cs 2 =v ih , v in =v il or v ih , read - 7 10 ma average operating current i cc1 cycle time=1 ? , 100% duty, i io =0ma cs 1 0.2v, cs 2 3 v cc -0.2v, v in 0.2v or v in 3 vcc -0.2v read - - 5 ma write - - 30 ma i cc2 cycle time=min, 100% duty, i io =0ma, cs 1 =v il , cs 2 =v ih , v in =v il or v ih - - 60 ma output low voltage v ol i ol =2.1ma - - 0.4 v output high voltage v oh i oh =-1.0ma 2.4 - - v standby current(ttl) i sb cs 1 =v ih , cs 2 =v il , other inputs =v il or v ih - - 3 ma standby current (cmos) i sb1 cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v or cs 2 0.2v - 1 10 1) m a
revision 0.0 KM68512B family cmos sram january 1998 5 advance ac characteristics (vcc=4.5~5.5v, KM68512B family : t a =0 to 70 c, KM68512Bi family : t a =-40 to 85 c) parameter list symbol speed bins units 55ns 70ns min max min max read read cycle time t rc 55 - 70 - ns address access time t aa - 55 - 70 ns chip select to output t co - 55 - 70 ns output enable to valid output t oe - 25 - 35 ns chip select to low-z output t lz 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns chip disable to high-z output t hz 0 20 0 25 ns output disable to high-z output t ohz 0 20 0 25 ns output hold from address change t oh 10 - 10 - ns write write cycle time t wc 55 - 70 - ns chip select to end of write t cw 45 - 60 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 45 - 60 - ns write pulse width t wp 40 - 55 - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 20 0 25 ns data to write time overlap t dw 20 - 30 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns c l 1) 1. including scope and jig capacitance ac operating conditions test conditions ( test load and input/output reference) input pulse level : 0.8 to 2.4v input rising and faling time : 5ns input and output reference voltage :1.5v output load(see right) : c l =100pf+1ttl data retention characteristics 1. cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v( cs 1 controlled) or cs 2 0.2v(cs 2 controlled). item symbol test condition min typ max unit vcc for data retention v dr cs 1 1) 3 vcc-0.2v 2.0 - 5.5 v data retention current i dr vcc=3.0v, cs 1 3 vcc-0.2v KM68512Bl-l - 0.5 10 m a KM68512Bli-l - - 15 data retention set-up time t sdr see data retention waveform 0 - - ms recovery time t rdr 5 - -
revision 0.0 KM68512B family cmos sram january 1998 6 advance address data out previous data valid data valid timming diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , we =v ih ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) data valid high-z cs 1 address oe data ou t notes ( read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. cs 2 t oh t aa t olz t lz t ohz t hz(1,2) t rc t co2 t oe t co1
revision 0.0 KM68512B family cmos sram january 1998 7 advance timing waveform of write cycle(1) ( we controlled) address cs 1 t cw(2) t wr(4) timing waveform of write cycle(2) ( cs 1 controlled) address cs 1 t wc t wr(4) t as(3) cs 2 t cw(2) t wp(1) t dw t dh t ow t whz data undefined data valid we data in data out t dw t dh data valid we data in data out high-z high-z cs 2 t wc t aw t as(3) t cw(2) t wp(1) t aw
revision 0.0 KM68512B family cmos sram january 1998 8 advance data retention wave form cs 1 controlled v cc 4.5v 2.2v v dr cs 1 gnd data retention mode cs 3 v cc - 0.2v t sdr t rdr timing waveform of write cycle(3) ( cs 1 controlled) address cs 1 t aw notes (write cycle) 1. a write occurs during the overlap of a low cs 1 , a high cs 2 and a low we . a write begins at the latest transition among cs 1 goes low, cs 2 going high and we going low : a write end at the earliest transition among cs 1 going high, cs 2 going low and we going high, t wp is measured from the begining of write to the end of write. 2. t cw is measured from the cs 1 going low or cs 2 going high to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr(1) applied in case a write ends as cs 1 or we going high t wr(2) applied in case a write ends as cs 2 going to low. cs 2 t wp(2) we data in data valid data out high-z high-z t cw(2) t wr(4) t wp(1) t dw t dh t as(3) t wc cs 2 controlled v cc 4.5v* 0.4v v dr cs 2 gnd data retention mode t sdr t rdr cs 2 0.2v
revision 0.0 KM68512B family cmos sram january 1998 9 advance package dimensions units : millimeters(inches) 32-thin small outline package type i (0820f) #32 1.00 0.10 0.039 0.004 max 8.40 0.331 0 . 1 0 m a x 0 . 0 0 4 m a x #1 0.50 ( ) 0.020 18.40 0.10 0.724 0.004 0.45 ~0.75 0.018 ~0.030 20.00 0.20 0.787 0.008 #17 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 #16
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